A few minutes after we published our brief about Navi 31’s frequency overclocking potential, a leak from Videocardz gives us a complete picture of the Navi 31 chip’s design details…and the fact that it is well cut for 3 Ghz. This diagram has the merit to make us visualize the originality of the design of the Navi 31 chip used for the RX 7900XTX and 7900XT.
Navi 31 is thus composed of a GCD (Graphics Compute Die) and six Memory Cache Dies (MCD). The external dies each house two 32-bit memory controllers, combined with a large L3 cache. These less critical memory and cache controllers are manufactured with a cheaper 6nm TSMC process, while the main graphics die uses 5nm from TSMC. As we’ve reiterated, AMD has been stingy with details at the launch of RDNA3. This leak brings us an interesting piece of information to complete our understanding of the new architecture.
Until then we knew that the full Navi 31 GPU would be equipped with 96 MB of L3 cache (Infinity Cache), but it was pitch black regarding the L0, L1 and L2 caches. These are mentioned in the slide above:
- L0 – 3 MB – 240% increase
- L1 – 3 MB – 300% increase
- L2 – 6 MB – 50% increase
- L3 (Infinity Cache) – 96 MB (32 MB less than Navi 21)
This leak which seems to come from an official presentation of AMD could announce others.
