Engraving: where does Intel stand against TSMC?


The arrival of Meteor Lake and its Intel 4, designed to compete with the TSMC N4 node, provides an opportunity to examine Intel’s roadmap for the miniaturization of its circuits. And to analyze its claim to become the king of etching finesse again by 2025.

Intel against TSMC
Pat Gelsinger, Intel CEO, presenting future generations of wafers materializing the next nodes of chip miniaturization (Intel Innovation 2023, San José, CA, USA). adrian BRANCO for Overclocking.com

Five engraving nodes in four years: more than a promise, it’s a mantra that has been recurring in Intel’s presentation slides for the past year. As soon as he took over the helm of this battered giant, Intel’s new boss, Pat Gelsinger, announced his ambitions to reclaim the crown of king of miniaturization that TSMC had “stolen” from Intel. Between 2022 and 2025, Intel aims to go from Intel 7 to Intel 18 A, i.e. an engraving jump every nine and a half months!

Today’s presentation of the details of its new generation of Meteor Lake chips is an opportunity for Intel to introduce its first chip element etched in Intel 4, its most accomplished etching finesse to date, which sits just opposite TSMC’s N4 node – sometimes called 4 nm, even if this nm designation is more complex to grasp than in the past.

But behind the production of Meteor Lake lies the question of Intel’s success: will the American giant be able to keep to its roadmap on the one hand, and steal its crown from TSMC (and Samsung, also in ambush) on the other? And behind these industrial issues lie questions of physical limits, economic sovereignty and the future of miniaturization.

An ambitious roadmap

Intel against TSMC

After naming its manufacturing nodes using nanometers to represent the minimum spacing between certain parts of its chips, Intel switched to the “nanometer equivalent ” favored by TSMC and Samsung. Intel’s five-node roadmap is thus expressed as follows: Intel 7 (7 nm equivalent), Intel 4, Intel 3 and the Intel 20A and Intel 18A. Two nodes that go down to the lower decimal place – the A stands for “Angstrom”, an obsolete unit equivalent to 10-10, ten times smaller than nanometers (10-9). For comparison, the equivalents are 2 nm and 1.8 nm. The latter is a good illustration of the difficulty of approaching the “fateful bar” of 1 nm.

Intel is now at Intel 4, a competitor to TSMC’s N4 nodes, which are available in several versions depending on requirements (pure performance, energy savings, etc.). Nodes are not TSMC’s state-of-the-art process, materialized last week by Apple’s A17 Pro chip, the first player to offer such a finely etched chip – and for good reason, the American company had reserved over 90% of worldwide production capacity!

Gravure Intel VS TSMC

Intel is still lagging behind TSMC, but should deliver the Intel 3 node (currently in the early stages of deployment) in the first half of 2024, followed by the “Angstrom” era nodes. At present, it’s not only impossible to predict whether Intel will keep up its pace in terms of miniaturization, but also whether its nodes will be on a par with those of the competition. More importantly, even if Intel did manage to produce in these nodes, it would also have to get up to speed in terms of yields to attract customers as part of its IDM 2.0 strategy (read below: Success will come from chasing customers).

Here are a few facts to bear in mind. On the one hand, Intel has never stopped working. If the American company has reached a ceiling with its 14 nm nodes in the production of its own chips, it’s because its roadmap foresaw a “quantum” leap towards EUV, with no intermediate steps. When Pat Gelsinger took over as head of Intel, he took all these elements and spread them out according to a timetable that was certainly ambitious, but not unrealistic – the technologies were already in the labs. And we’re talking here not only about etching finesse, but also about the introduction of chip design technologies – RibbonFET for transistor structure, PowerVIA which modifies the power supply principle to reduce energy consumption, and so on.

But there’s one last important fact: Intel is going to have to fight TSMC and physics.

The difficult art of miniaturization and the weight of the champion

taille Gravure Intel

Why does halving the number of engraving nodes translate into tens of percent gains, rather than an automatic x2? Because sizes expressed in nanometers only concern one element of the chips. That is, the minimum spacing between two logic gates. However, other elements, such as the ultra-fast memory embedded inside processors (SRAM), do not follow the same path. In fact, it’s much worse than that: for physical reasons – memory has to retain information, and therefore charges, while charges circulate in the transistors linked to calculations – the reduction in SRAM size has reached a ceiling.

Evolution gravure
Not all chip elements shrink as efficiently. While the logic part – the transistors that form the famous logic gates – have been greatly reduced in size, the same cannot be said of the SRAM. ©WikiChip

To this physical challenge that Intel and its competitors all face, we must also add an important element: TSMC has always been a subcontractor. And to cope with the horde of customers, it has created an entire software ecosystem with semiconductor development software publishers such as Synopsys, Cadence and Siemens (known as EDMs, for Electronic Design Manufacturing). Far from being an afterthought, these software packages include production “libraries” that improve over time. When it comes to GPUs alone, TSMC is by far the world champion. Whether it’s AMD’s RDNA3 (Radeon RX7000), Nvidia’s Ada Lovelace (RTX4000) or Intel’s Arc (yes, yes), all these chips come out of the Taiwanese company’s factories – and the same goes for console CPUs and GPUs (PlayStation, Xbox Series)… As for the Meteor Lake GPU brick!

To succeed, Intel will therefore have to put its heart and soul into building libraries for these design programs – and this is already well underway, with the partnership with Cadence on Intel 3 and 18A nodes. Alongside this industrial and software work, Intel will also have to concentrate on a battle that its factories are not yet accustomed to waging: finding and winning over customers.

Success will depend on the hunt for customers

Future usine Intel Europe gravure
Architect’s view of the future Magdeburg factory © Intel

Rome wasn’t built in a day, and TSMC didn’t become the king of etching in the blink of an eye. If the future of cutting-edge technologies is inherently uncertain, we can find food for thought by looking in the rear-view mirror. If the Taiwanese succeeded in overtaking the Americans, it was thanks to the quality of their engineers, of course. Engineers who were only able to demonstrate their talent for one fundamental reason: they worked hard! By positioning itself as a neutral player that does not develop chips in its own name, TSMC has attracted semiconductor designers from all over the world. As a result, TSMC boasts over 500 customers, the most famous of which is Apple. Apple and its smartphone rivals (Qualcomm, MediaTek and formerly Huawei) have enormous physical constraints, order huge volumes and have deep pockets.

However talented the engineers at Intel’s fabs may be, their success will depend on their ability to attract the first customers to their factories. To enable them to get to grips with their new profession. In other words, not just producing “for the house”, but knowing how to seduce, listen and put themselves at the service of customers. Regardless of the name itself, the rise of another player alongside TSMC and Samsung is good news… for everyone.

The benefits of a third player: independence and resilience

les usines de gravure d'Intel
The sun never sets on Intel’s factories © Intel

As the only chip designer and manufacturer alongside Samsung, Intel’s mastery of the x86 architecture made it the world’s only IDM, or “total” chip designer. New boss P. Gelsinger’s IDM 2.0 plan aims not only to maintain Intel’s dominance in PC and server chips, but also to position itself as a leading foundry in the face of TSMC and Samsung. These two giants are the biggest chip producers for others, and the only ones to master EUV mass production.

If Intel can already match its Asian rivals, this will mean less potential dependence for Westerners on factories that are all located on the same continent – COVID demonstrated the importance of supply chain redundancy. With factories not only in the USA, but also in China, Malaysia, Puerto Rico, Israel, Ireland, and soon in Germany and Poland, Intel is the only geostrategically global and Western-centric player. By contrast, TSMC’s power is fully expressed in Taiwan (as much for reasons of industrial concentration as in the context of the local Silicon Shield doctrine), with minor fabs and a major fab on the way in the USA. As for Samsung, apart from the production of SSD controllers in the USA and a few small sites here and there, the Korean company, like its Taiwanese competitor, is essentially focused on its home territory.

Intel’s success stimulates competition and brings in cash

ASML acteur clé dans la compétition gravure TSMC vs Intel
ASML’s future High NA (0.55 NA) EUV scanners under development here will cost in the region of $350-400 million apiece (or even more). That’s almost three times the price of the first EUV scanners, and future generations are expected to cost even more… © ASML

In addition to these “geopolitical” aspects, we must also add a major element for the future of circuit miniaturization: the field needs competition and money. Competition on the one hand, because since the transition to the EUV etching era, only three players are in the ultra-miniaturization race, the others – UMC, GlobalFounderies, STMicroelectronics, Vanguard, etc. – having all thrown in the towel. – The others – UMC, GlobalFounderies, STMicroelectronics, Vanguard, etc. – have all thrown in the towel to focus on niche markets (silicon carbide, photonics, etc.). However, if one or two players were to fall behind, innovation in chip size reduction would be severely hampered.

Another important factor that is sometimes overlooked is money. More specifically, investment in R&D. Investments that are as high as the price of lithography scanners (or steppers), i.e. exploding. The finer the circuits need to be etched, the greater the constraints, and the higher the price of the machines – and the chips in return – becomes. While ASML’s first EUV steppers already commanded a record price of €150 million apiece, the new “High-NA” versions are said to cost in excess of €300 million. With an estimated initial potential for nanometer etching.

Theoretically, there is a machine that can go even further: the Hyper NA version. But in the words of ASML’s CEO in a recent interview with Dutch media, “I don’t know if it will ever be economically viable”. As a long-standing partner of ASML, and at the forefront of R&D around the High NA machines due to come on stream as early as 2024, notably at the Lexip site in Ireland, Intel has enormous R&D potential. This, combined with the deep pockets of Samsung and TSMC, could help to continue funding research in a field where circuits will, one day, probably be no more than an atom wide.