With Zen 5, we should see a considerable improvement in processor performance on tasks using AVX-512 instructions. In fact, thanks to a new FPU, performance could be up a good 40% on Zen 4 (Ryzen 7000).
Zen 5: 40% performances on AVX-512 tasks?
While Zen 4 exploited a dual 256-bit FPU for AVX-512 task execution, this will no longer be the case with Ryzen 9000. In fact, according to Moore’s Law is Dead, AMD has revised this aspect of its processors, opting for a 512-bit FPU. This should considerably improve performance in workloads taking advantage of AVX-512 and VNNI instructions, such as artificial intelligence… A crucial point in view of its increasingly important presence.
However, changing the FPU is all well and good, but behind the scenes, AMD has overhauled everything that goes with it for better processing capability. Basically, we learn that the reds have increased the capacity of the L1 DTLB(Data Translation Lookaside Buffer) and that load-store queues have been enlarged. As for caches, L1 Data bandwidth has been doubled, while capacity has been increased by 50%. The number of execution pipelines has been increased from 8 to 10, and MADD FPU latency has been reduced by one cycle.
To put it simply, these processors are much more responsive and will handle complex workloads more efficiently.
