Home News Hardware News Zen 6: CPUs expected to exceed 6.5 GHz!

Zen 6: CPUs expected to exceed 6.5 GHz!

0
Overclocking.com video

If Nova Lake represents the next generation of CPUs from Intel, Zen 6 is the same thing, but for AMD. Today, we’re seeing a new batch of rumors regarding AMD’s upcoming processors. According to Moore’s Law is Dead, the next generation of AMD processors will exceed 6.5 GHz in operating frequency. Apparently, the leaker is 100% convinced of this. We’ll have to wait and see how it turns out, but he’s also sharing other interesting information.

Zen 6: heading toward very high frequencies!

Over 6.5 GHz, 100% certain: 

AMD Zen 6

This isn’t the first time we’ve heard about these very high frequencies on Ryzen processors. In fact, last June, the same leaker announced that the next generation of AMD CPUs would run “well beyond” 6 GHz. Clearly, he’s sticking to his guns, stating that it will be over 6.5 GHz and that he’s “100%” sure of it.

We’ll have to wait and see, but just like last time, we have some reservations about these claims of particularly high frequencies. After all, AMD Ryzen CPUs aren’t chips that reach insanely high frequencies, as we often see with Intel, for example. Furthermore, currently, a Ryzen 7 9700X has a boost clock of 5.5 GHz, which would represent a 1 GHz increase at stock settings. That seems very optimistic to us… But perhaps AMD has improved its architecture to facilitate overclocking—who knows. In any case, take this with a grain of salt.

Up to 24 cores and an increase in L3 cache! 

However, what seems more likely is the claim that Zen 6 will offer CPUs with 24 cores and increased L3 cache. Indeed, these models will feature not 8 cores per CCD, but 12. The amount of L3 cache would then increase from 32 MB to 48 MB per CCD as well. Thus, the flagship model, a hypothetical Ryzen 9 10950X, could offer 24 cores, 48 threads, and 96 MB of L3 cache in its base configuration. Better yet, the X3D versions could feature a 3D V-Cache with a total of 192 MB of L3. A hypothetical X3D2 could even go up to 288 MB of L3.

Otherwise, with Zen 6, there is also talk of die bridges to ensure the connection between the CCDs and the CPU’s I/O die. This method would improve the interconnect speed between the different parts of the processor and thus reduce latency within the chip itself.

However, it appears that AMD has already taped out its B0 stepping for Zen 6. But this wouldn’t happen without a hitch. According to the leaker, a problem has been discovered, and the company faces two choices: delay production to perform a new tape-out, or patch the issue via a microcode update, which would impact performance. Even if it were a minor issue, the company is reportedly being cautious, as the pressure is mounting, especially with Intel waiting in the wings with Nova Lake.