The exciting thing about the world of computing is that from one week to the next, things change completely. Last week, for example, we learned that Intel’s 18A process yields were disastrous: 10%. However, the semiconductor manufacturing process is a complex one. And talking about yields alone doesn’t make much sense unless you take into account the size of the chip or the defect density during production.
Is 18A a disaster? Yes, but no.
Last week, for example, we learned of a report claiming a catastrophic yield of 10%… At the same time, we learned of a 60% yield for Panther Lake. In reality, you have to take into account the size of the chips to be burnt, but also the defect density. Yes, the larger the chip, the more space it takes up on the silicon wafer, and the higher the defect density, the lower the yield. Conversely, the smaller the chip, the better the yield.
TechpowerUp has made some estimates using the SemiAnalysis Die Yield Calculator with large and small chips. On a huge 858 mm² chip with a defect density of D0<0.40 expressed in cm² (announced by Intel), it appears that the yield varies from 3.23% to 22.56% depending on the model applied. Yes, there are different models for calculating yields, taking different parameters into account.
In contrast, smaller chips, such as the die of a Panther Lake CPU (8.004×14.288 mm) show efficiencies of between 50 and 64.4%, depending on whether you apply Moore’s or Murphy’s model. As for the GPU die (53.6 mm²), the efficiency is even better, between 60% and 81%.
However, it should also be borne in mind that processes mature and defect density can be improved over time. Similarly, the design of the chip also plays a role in efficiency, depending on the positioning of the transistors, the type of transistor, and so on. Moreover, when a foundry launches a new process, very often it’s small chips that are produced with it, while the larger components arrive as the process matures.
Clearly, things are going well at Intel, and the company could well launch its 18A on schedule in 2025. Pat Gelsinger’s publications on X, Intel’s former CEO, also point in this direction.
