Intel unveiled the technical specifications of its new Wildcat Lake architecture yesterday at the Hot Chips 2026 conference. Positioned as an alternative to the MacBook Neo, this entry-level chip is built on the 18A process node and incorporates the UCIe (Universal Chiplet Interconnect Express) specification to optimize costs and communication between chips.
Wildcat Lake: An Innovative Multi-Chip Package (MCP) Architecture
Lance Hacking, chief engineer of the Wildcat Lake project, explained that the company had to choose between a monolithic design and a basic Multi-Chip Package (MCP) to achieve a competitive price. Although Intel’s advanced Foveros packaging technology was available, it was not suitable for meeting the budget requirements. It was therefore the integration of UCIe that made Wildcat Lake possible.
Unlike traditional N-1 designs that use older platforms, Wildcat Lake adopts Intel’s latest and most expensive designs. The compute core uses the 18A node, while the I/O die is manufactured by TSMC on the N6 node. This approach required a UCIe interconnect 70% larger than that of Panther Lake, but Intel believes the cost savings justified this increase in area.
Drastic optimizations to reduce power consumption and costs
Power management was a critical issue, especially for a chip intended for light workloads. Intel implemented a buffer to store display panel refresh rates during periods of inactivity, thereby reducing power demand. To save space on the compute die, Intel reduced the number of Xe cores from four to two, removed the dedicated ray tracing accelerator, and reduced the number of NPU tiles from three to one.
The memory subsystem has also been limited to a 64-bit bus, with reduced bandwidth and capacity. On the I/O die, Intel reclaimed 15% of the area by removing the camera PHY, reducing PCIe and USB support, and streamlining the audio engine. Camera support has been completely removed, forcing manufacturers to integrate their own controllers.
Finally, the UCIe transfer rate has been limited to 8 GT/s, well below the 64 GT/s maximum specified in the UCIe 3.0 standard. This restriction enables support for PCIe 4 SSDs and 4K60 displays while reducing the bit error rate and eliminating certain error correction schemes.
A Cost- and Yield-Focused Strategy for OEMs
Reducing the number of compute and I/O dies saves on raw materials and improves yield without requiring advanced packaging. Intel uses Wildcat Lake binning to offer different SKUs, allowing, for example, a single functional P-core to be sold as a Core 3 304. However, binning is not applied to LPE and I/O clusters, which are critical components of the architecture.
Intel has also integrated Wi-Fi 7 and a USB PD controller to reduce costs for OEMs. The use of a narrower memory bus and a six-layer motherboard instead of an eight-layer one also contributes to cost savings. Despite these efforts, a dedicated power path for the LPE cluster has been retained to ensure autonomy under light workloads.
