After being leaked almost a year ago, the support of twelve memory controllers on Genoa is confirmed by a Linux patch.
Up to 12TB and 5200 MT/s for DDR5 on Genoa
With the Zen 4 architecture and the arrival of DDR5, AMD will increase the bandwidth and memory capacity of its next server platform. The SP5 socket hosting the Genoa processors. We should see the increase of the number of memory controllers from 8 to 12, confirmed a few days ago by a Linux patch. This patch informs us that the number of memory controllers for Genoa has increased to 12, but also that the processor will support two other types of memory, namely LPDDR5 and RDDR5. 
This information, although confirmed today, was leaked several months ago, notably by ExecuFix but also with the Gigabyteleak in August where several documents had leaked. These confirmed that the Genoa processors would manage twelve memory controllers with DDR5. 
The Gigabyte documents also confirmed support for up to 12TB of memory per processor at 4000 MT/s or 5200 MT/s with 3TB of memory. As a reminder, the EPYC Genoa processors are based on the Zen 4 architecture and are expected to arrive in late 2022. Their main characteristics are a maximum of 96 cores, 128 lines of PCIe 5.0, a TDP of 320W (configurable to 400W) and all on the new SP5 socket in LGA-6096.
