Rumor after rumor continues to surround Nova Lake. After an initial article on the use of a sixth-generation NPU, we now turn to a rumour concerning support or otherwise for AVX10, APX and AMX. A GCC compiler patch seems to indicate that this is not the case.
Nova Lake: what about support for AVX10, APX and AMX?
Normally, at this stage of development, a number of things have been decided for Nova Lake. Logically, core design is complete, as is the NPU part, and the same should apply to supported instruction sets. And that’s where the famous GCC compiler patch comes in, which makes no mention of support for AVX10, APX and AMX, which can be very useful in certain application areas. These include content creation, certain AI-related tasks and encoding/decoding. These instructions are said to be exclusive to Xeon server processors.
On the other hand, this contradicts what was said last August about “future Core CPUs ” supporting AVX10.2. All this was discovered in a oneDNN software library. In the end, we’ll have to be patient and wait for other similar patches to be released, or for Intel to confirm the instruction sets supported by its processors. But for that, we’ll certainly have to wait until launch.
In the meantime, AMD has a head start on the Blues on this front, since, let’s not forget, Ryzen 9000s fully support AVX-512. This offers performance gains for applications exploiting this type of instruction, whereas in the case of Nova Lake, it’s not impossible to end up with a large 52-core CPU that doesn’t support fast matrix and vector acceleration.