At the moment, little is known about AMD’s upcoming Zen 5 architecture, which is expected to arrive in the second half of 2024. So please note that the elements here are only rumors. However, the official communication from AMD allows us to understand that with Zen 5, the future Ryzen 8000 processors and the Epyc Turin range, will have a major overhaul of the Zen architecture introduced in 2017. The main axis of improvement will concern a reworked interface, a larger instruction set, a larger cache and especially an improvement in latency. According to some leaks, Zen 5 will introduce a new on-die core-to-core interconnect called Ladder L3 Fabric. It should provide a large part of the performance improvements by itself.
Ryzen 8000: a profound change?
According to the information mentioned in the AdoredTV video, Zen 5 will feature a unique core interconnect called Ladder L3 Fabric. With this new design, each core is directly connected to the other. Adjacent cores are connected using a common ladder bus, which in turn is connected to the opposite bus via seven high-speed links (diagram here from the video). Again, the logic here would be to improve latency between cores and in turn performance in games in particular, the Achilles heel of the latest “big” Ryzen.
We will also have to count on an improvement of the L3 cache and Zen 5 could double or perhaps triple the amount of L2 cache per core to 2 MB or 3 MB cache per core to 2 MB or 3 MB.
In the site of other rumors, we also mention for Ryzen 8000 and Zen 5 chips in general the following advances:
- Zen 5 chips adopting a hybrid design.
- The number of cores will increase significantly, for example to 32 cores.
- L1 cache will increase.